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Johnson DE, Marsland JS, Eccleston W. Neural network implementation using a single MOST per synapse. IEEE Trans Neural Netw. 1995;6(4):1008-11doi: 10.1109/72.392265.
Johnson, D. E., Marsland, J. S., & Eccleston, W. (1995). Neural network implementation using a single MOST per synapse. IEEE transactions on neural networks, 6(4), 1008-11. https://doi.org/10.1109/72.392265
Johnson, D E, et al. "Neural network implementation using a single MOST per synapse." IEEE transactions on neural networks vol. 6,4 (1995): 1008-11. doi: https://doi.org/10.1109/72.392265
Johnson DE, Marsland JS, Eccleston W. Neural network implementation using a single MOST per synapse. IEEE Trans Neural Netw. 1995;6(4):1008-11. doi: 10.1109/72.392265. PMID: 18263390.
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IEEE Trans Neural Netw. 1995;6(4):1008-11. doi: 10.1109/72.392265.

Neural network implementation using a single MOST per synapse.

IEEE transactions on neural networks

D E Johnson, J S Marsland, W Eccleston

Affiliations

  1. Dept. of Electr. Eng. and Electron., Liverpool Univ.

PMID: 18263390 DOI: 10.1109/72.392265

Abstract

A VLSI implementation of an artificial neural network using a single n-channel MOS (metal-oxide semiconductor) transistor per synapse is investigated. The simplicity of the design is achieved by using pulse width modulation to represent neural activity and by using a novel technique to manipulate negative weights. A simple multilayer perceptron (MLP) network was simulated using the SPICE circuit simulator and the performance of a hardware realization of the same MLP network was measured. Simulations and measurements are shown to agree well.

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