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Amsinck CJ, Di Spigna NH, Nackashi DP, et al. Scaling constraints in nanoelectronic random-access memories. Nanotechnology. 2005;16(10):2251-60doi: 10.1088/0957-4484/16/10/047.
Amsinck, C. J., Di Spigna, N. H., Nackashi, D. P., & Franzon, P. D. (2005). Scaling constraints in nanoelectronic random-access memories. Nanotechnology, 16(10), 2251-60. https://doi.org/10.1088/0957-4484/16/10/047
Amsinck, Christian J, et al. "Scaling constraints in nanoelectronic random-access memories." Nanotechnology vol. 16,10 (2005): 2251-60. doi: https://doi.org/10.1088/0957-4484/16/10/047
Amsinck CJ, Di Spigna NH, Nackashi DP, Franzon PD. Scaling constraints in nanoelectronic random-access memories. Nanotechnology. 2005 Oct;16(10):2251-60. doi: 10.1088/0957-4484/16/10/047. Epub 2005 Aug 26. PMID: 20818005.
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Nanotechnology. 2005 Oct;16(10):2251-60. doi: 10.1088/0957-4484/16/10/047. Epub 2005 Aug 26.

Scaling constraints in nanoelectronic random-access memories.

Nanotechnology

Christian J Amsinck, Neil H Di Spigna, David P Nackashi, Paul D Franzon

Affiliations

  1. North Carolina State University, PO Box 7911, Raleigh, NC 27695-7911, USA.

PMID: 20818005 DOI: 10.1088/0957-4484/16/10/047

Abstract

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.

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