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Burke AM, Carrad DJ, Gluschke JG, et al. InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments. Nano Lett. 2015;15(5):2836-43doi: 10.1021/nl5043243.
Burke, A. M., Carrad, D. J., Gluschke, J. G., Storm, K., Fahlvik Svensson, S., Linke, H., Samuelson, L., & Micolich, A. P. (2015). InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments. Nano letters, 15(5), 2836-43. https://doi.org/10.1021/nl5043243
Burke, A M, et al. "InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments." Nano letters vol. 15,5 (2015): 2836-43. doi: https://doi.org/10.1021/nl5043243
Burke AM, Carrad DJ, Gluschke JG, Storm K, Fahlvik Svensson S, Linke H, Samuelson L, Micolich AP. InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments. Nano Lett. 2015 May 13;15(5):2836-43. doi: 10.1021/nl5043243. Epub 2015 Apr 21. PMID: 25879492.
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Nano Lett. 2015 May 13;15(5):2836-43. doi: 10.1021/nl5043243. Epub 2015 Apr 21.

InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments.

Nano letters

A M Burke, D J Carrad, J G Gluschke, K Storm, S Fahlvik Svensson, H Linke, L Samuelson, A P Micolich

Affiliations

  1. †School of Physics, University of New South Wales, Sydney, NSW 2052, Australia.
  2. ‡Solid State Physics/Nanometer Structure Consortium (nmC@LU), Lund University, SE-221 00 Lund, Sweden.

PMID: 25879492 DOI: 10.1021/nl5043243

Abstract

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

Keywords: III−V nanowires; field-effect transistor; gate-all-around; wrap-gate

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