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Roy F, Suler A, Dalleau T, et al. Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications. Sensors (Basel). 2020;20(3)doi: 10.3390/s20030727.
Roy, F., Suler, A., Dalleau, T., Duru, R., Benoit, D., Arnaud, J., Cazaux, Y., Chaton, C., Montes, L., Morfouli, P., & Lu, G. N. (2020). Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications. Sensors (Basel, Switzerland), 20(3), . https://doi.org/10.3390/s20030727
Roy, Francois, et al. "Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications." Sensors (Basel, Switzerland) vol. 20,3 (2020). doi: https://doi.org/10.3390/s20030727
Roy F, Suler A, Dalleau T, Duru R, Benoit D, Arnaud J, Cazaux Y, Chaton C, Montes L, Morfouli P, Lu GN. Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications. Sensors (Basel). 2020 Jan 28;20(3). doi: 10.3390/s20030727. PMID: 32012978; PMCID: PMC7038367.
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Sensors (Basel). 2020 Jan 28;20(3). doi: 10.3390/s20030727.

Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications.

Sensors (Basel, Switzerland)

Francois Roy, Andrej Suler, Thomas Dalleau, Romain Duru, Daniel Benoit, Jihane Arnaud, Yvon Cazaux, Catherine Chaton, Laurent Montes, Panagiota Morfouli, Guo-Neng Lu

Affiliations

  1. STMicroelectronics, 850 Rue Jean Monnet, 38921 Colles, France.
  2. IMEP-LaHC, Université Grenoble Alpes, 38016 Grenoble, France.
  3. INL, Université Claude Bernard Lyon 1, 69622 Villeurbanne, France.
  4. LETI-CEA Tech, 17 rue des Martyrs, 38054 Grenoble, France.

PMID: 32012978 PMCID: PMC7038367 DOI: 10.3390/s20030727

Abstract

Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide-nitride-oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

Keywords: CMOS image sensor (CIS); capacitive deep trench isolation; dark current; photo gate; pixel; surface passivation; transfer gate

References

  1. Sensors (Basel). 2018 Jul 20;18(7): - PubMed

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