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Faria R, Kaiser J, Camsari KY, et al. Hardware Design for Autonomous Bayesian Networks. Front Comput Neurosci. 2021;15:584797doi: 10.3389/fncom.2021.584797.
Faria, R., Kaiser, J., Camsari, K. Y., & Datta, S. (2021). Hardware Design for Autonomous Bayesian Networks. Frontiers in computational neuroscience, 15584797. https://doi.org/10.3389/fncom.2021.584797
Faria, Rafatul, et al. "Hardware Design for Autonomous Bayesian Networks." Frontiers in computational neuroscience vol. 15 (2021): 584797. doi: https://doi.org/10.3389/fncom.2021.584797
Faria R, Kaiser J, Camsari KY, Datta S. Hardware Design for Autonomous Bayesian Networks. Front Comput Neurosci. 2021 Mar 08;15:584797. doi: 10.3389/fncom.2021.584797. eCollection 2021. PMID: 33762919; PMCID: PMC7982658.
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Front Comput Neurosci. 2021 Mar 08;15:584797. doi: 10.3389/fncom.2021.584797. eCollection 2021.

Hardware Design for Autonomous Bayesian Networks.

Frontiers in computational neuroscience

Rafatul Faria, Jan Kaiser, Kerem Y Camsari, Supriyo Datta

Affiliations

  1. Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, United States.
  2. Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA, United States.

PMID: 33762919 PMCID: PMC7982658 DOI: 10.3389/fncom.2021.584797

Abstract

Directed acyclic graphs or Bayesian networks that are popular in many AI-related sectors for probabilistic inference and causal reasoning can be mapped to probabilistic circuits built out of probabilistic bits (p-bits), analogous to binary stochastic neurons of stochastic artificial neural networks. In order to satisfy standard statistical results, individual p-bits not only need to be updated sequentially but also in order from the parent to the child nodes, necessitating the use of sequencers in software implementations. In this article, we first use SPICE simulations to show that an autonomous hardware Bayesian network can operate correctly without any clocks or sequencers, but only if the individual p-bits are appropriately designed. We then present a simple behavioral model of the autonomous hardware illustrating the essential characteristics needed for correct sequencer-free operation. This model is also benchmarked against SPICE simulations and can be used to simulate large-scale networks. Our results could be useful in the design of hardware accelerators that use energy-efficient building blocks suited for low-level implementations of Bayesian networks. The autonomous massively parallel operation of our proposed stochastic hardware has biological relevance since neural dynamics in brain is also stochastic and autonomous by nature.

Copyright © 2021 Faria, Kaiser, Camsari and Datta.

Keywords: Bayesian network; binary stochastic neuron; inference; magnetic tunnel junction; probabilistic spin logic

Conflict of interest statement

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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