A worst case timing analysis technique for multiple-issue machines. Kim J, Lim SS, Min SL. SS Lim, JH Han, J Kim, SL Min - Proceedings 19th IEEE Real …, 1998 - ieeexplore.ieee.org GSID: slcEaXhQI0MJ
Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis. Ferdinand C. H Theiling, C Ferdinand - Proceedings 19th IEEE Real-Time …, 1998 - ieeexplore.ieee.org GSID: cPkoz4bbcQ0J
The influence of processor architecture on the design and the results of WCET tools. [No authors listed] GSID: N430Rz4ZFDkJ
Abstract interpretation based formal methods and future challenges. [No authors listed] GSID: JqmO3Lpxf0IJ
Fast and precise WCET prediction by separated cache and path analyses. [No authors listed] GSID: Ob1JN8fKUicJ
