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Oh, S., Kim, T. G., Cho, J., & Bozorgzadeh, E. (2008). Speculative loop-pipelining in binary translation for hardware acceleration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(3), 409-422.
Oh, Sejong, et al. "Speculative loop-pipelining in binary translation for hardware acceleration." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27.3 (2008): 409-422.
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S Oh, TG Kim, J Cho… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org

Speculative loop-pipelining in binary translation for hardware acceleration.

pipeline programs

Cho, Kim

GSID: 6N6dvv85ZeYJ

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Multimedia and DSP applications have several computationally intensive kernels which are often off loaded and accelerated by application-specific hardware. This paper presents a …

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