CCF:SMALL:TIMING VARIATION RESILIENT SIGNAL PROCESSING: HARDWARE-ASSISTED CROSS-LAYER ADAPTATION.

[No authors listed]

UIID-NSF: 541

Abstract

In this research, a new vertically integrated cross-layer timing variation resilience methodology at the algorithm, microarchitecture and circuit levels, with "hardware-assistance" from the latter two levels is proposed. This addresses the effects of process variations and random delay defects in modern deeply scaled technologies as well as the effects of electrical bugs. At the highest level of the layer stack, the project considers algorithmic level workload adaptation as well as adaptation to intermittent errors in the underlying hardware due to low-power/high-speed pipeline and arithmetic unit operation. A key contribution of this research is a novel way to accurately determine when the logic and arithmetic units of pipeline stages have finished computation. This uses concepts from wave pipelined operation of logic circuits and allows activity completion detection within nearly a single or a few gate delays. Such completion sensing allows pipeline stages to "borrow" or "lend" time much more effectively than currently used synchronously clocked pipelines. In addition, backup error detection mechanisms allow the processor pipeline to operate reliably even when there is some kind of malfunction in the completion sensing circuitry. A vertically integrated control algorithm is used to modulate power vs. performance vs. timing error resilience at the circuit, microarchitecture and algorithm (video compression) levels to deliver the desired quality of service at the required video throughput with minimum power consumption. Through this research effort, the development of courses at GaTech in embedded DSP design and test, and yield management research under extreme process variations will be greatly facilitated. The PIs will develop a set of teaching materials on power management and error resilience in real-time digital signal processing systems. The PIs will make maximum effort to involve undergraduate students from the Summer Undergraduate Research Experience for minorities (SURE) program in the proposed research. It will also be possible to involve senior undergraduate project students in this research through targeted advisement. They will participate in H.O.T. Days@ Georgia Tech, a one-week long summer program designed to introduce high school students to electrical and computer engineering concepts. The key involvement will be in working with robots (LEGO Mindstorm, simple functions). Both Georgia Tech and Auburn University aggressively encourage participation of undergraduate students, as well as women and minorities in research. Auburn's participation in the project will also improve the research capabilities of Alabama, an EPSCOR state. Additionally, several master's students from the Historically Black Tuskegee University located near Auburn will take graduate courses at Auburn University. The best prepared among these students will be encouraged to join the project and Ph.D. programs at the participating universities. Thus, funding for this project will support the goals of recruiting more U.S. citizens, women and minorities to graduate programs.

Other Details

• Award Instrument: Standard Grant
• Email: [email protected]
• Organization: Georgia Tech Research Corporation
• Other Investigators: Daniel Conte de Leon
• Primary Investigator: Abhijit Chatterjee
• Program(s): DES AUTO FOR MICRO and NANO SYST
• Start Date: 09/01/2013