Display options
Share it on
Full text links
View full text

GA Reis, J Chang, N Vachharajani… - … symposium on Code …, 2005 - ieeexplore.ieee.org

SWIFT: Software implemented fault tolerance.

Build and Broaden 3.0 AND Program Evaluation

Chang, Reis, Vachharajani

GSID: eYSKXKLsRgsJ

Excerpt

To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. …

Similar articles

Chang J, Rangan R, Reis GA, Vachharajani N.
GA Reis, J Chang, N Vachharajani, R Rangan… - ACM Transactions on …, 2005 - dl.acm.org
GSID: sr0CrrLO7W4J

Cited by