J Nanosci Nanotechnol. 2015 Oct;15(10):7430-5. doi: 10.1166/jnn.2015.11146.

Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations.

Journal of nanoscience and nanotechnology

Young Jun Yoon, Hye Rim Eun, Jae Hwa Seo, Hee-Sung Kang, Seong Min Lee, Jeongmin Lee, Seongjae Cho, Heung-Sik Tae, Jung-Hee Lee, In Man Kang

PMID: 26726346 DOI: 10.1166/jnn.2015.11146

Abstract

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.

Publication Types

• Journal Article
• Research Support, Non-U.S. Gov't