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Wu TT, Huang WH, Yang CC, et al. High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits. Sci Rep. 2017;7(1):1368doi: 10.1038/s41598-017-01012-y.
Wu, T. T., Huang, W. H., Yang, C. C., Chen, H. C., Hsieh, T. Y., Lin, W. S., Kao, M. H., Chen, C. H., Yao, J. Y., Jian, Y. L., Hsu, C. C., Lin, K. L., Shen, C. H., Chueh, Y. L., & Shieh, J. M. (2017). High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits. Scientific reports, 7(1), 1368. https://doi.org/10.1038/s41598-017-01012-y
Wu, Tsung-Ta, et al. "High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits." Scientific reports vol. 7,1 (2017): 1368. doi: https://doi.org/10.1038/s41598-017-01012-y
Wu TT, Huang WH, Yang CC, Chen HC, Hsieh TY, Lin WS, Kao MH, Chen CH, Yao JY, Jian YL, Hsu CC, Lin KL, Shen CH, Chueh YL, Shieh JM. High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits. Sci Rep. 2017 May 02;7(1):1368. doi: 10.1038/s41598-017-01012-y. PMID: 28465531; PMCID: PMC5431052.
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